1. Field of the Invention
The present invention relates generally to a semiconductor structure and a process thereof, and more specifically to a semiconductor structure and a process thereof that integrates capacitors and transistors.
2. Description of the Prior Art
Each capacitor in a semiconductor component usually includes two electrodes and a dielectric layer between the two electrodes. This structure has been widely used in many semiconductor components such as dynamic random access memories (DRAM). A capacitor process often includes the following steps: a conductive layer is formed on a substrate and is patterned to forma lower electrode of the capacitor; a dielectric layer is formed on the lower electrode; then, another conductive layer covers the dielectric layer to form the capacitor.
The materials of the electrodes may include polysilicon, polycide and metal. Thus, there are three fabricating methods for forming three kinds of capacitors in semiconductor wafer industry: Metal-insulator-Metal (MIM) capacitors, Poly-insulator-Poly (PIP) capacitors and Metal Oxide Semiconductor (MOS) capacitors to be compatible with CMOS transistor processes, for achieving process simplification. A MIM capacitor is constituted by two metals serving as electrodes. A PIP capacitor is constituted by two polysilicon layers serving as electrodes. A MOS capacitor is constituted by connecting a source and a corresponding drain of a MOS transistor serving as one electrode while a gate of the MOS transistor serves as the other electrode.
As the integration of an integrated circuit increases and sizes of its semiconductor components shrink, it becomes a great issue to integrate these components such as capacitors and transistors in the industry to achieve a desired capacitance and an operation power, and simplify processes and reduce processing costs.